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[Embeded-SCM Develop] ref-ddr-sdram-verilog.zip

Description: sdram的verilog的源码实现
Platform: | Size: 903683 | Author: | Hits:

[Other resource] ddr_sdr_V1_1

Description: ddr verilog代码,实现DDR内存控制，是一个高效率的程序
Platform: | Size: 39298 | Author: liujun | Hits:

[Other] 128Mb_ddr

Description: 128Mb DDR verilog源程序
Platform: | Size: 23340 | Author: tiantian | Hits:

[VHDL-FPGA-Verilog] ddr_verilog_xilinx

Description: 该程序是在xilinx的FPGA上实现DDR_SDRAM接口，程序是用verylog语言写的-that the procedure was in Xilinx FPGA to achieve DDR_SDRAM interface, procedures used to write the language verylog
Platform: | Size: 23552 | Author: 冯伟 | Hits:

[VHDL-FPGA-Verilog] xapp935

Description: ddr2 controller, verilog source code from xilinx
Platform: | Size: 347136 | Author: Hubert | Hits:

[VHDL-FPGA-Verilog] Xil3SD1800A_MIG_simplifiedUI_vlog_v92

Description: verilog 实现的spartan 3A dsp start kit DDR2 SDRAM 控制器-verilog achieved spartan 3A dsp start kit DDR2 SDRAM controller
Platform: | Size: 908288 | Author: ma yirong | Hits:

[VHDL-FPGA-Verilog] ddr_verilog_xilinx

Description: xilinx的ddr sdram控制器文档-xilinx of ddr sdram controller documentation
Platform: | Size: 678912 | Author: liujie | Hits:

[Other] yuqix_datum

Description: i2cinterface.v是我自己写的一段verilog代码，在接口为I2C接口的芯片设计中用到。送去流过片，仅作参考用。 debussy和modelsim协同仿真.txt 用于debussy和modelsim协同仿真时参考 RTL Coding and Optimization Guide for use with Design Compiler.pdf 数提讲座（1）.wmv 数提讲座（2）.wmv这两个视频和一篇文档对数字IC前端设计师的设计提高很有帮助，如果你觉得你到瓶颈状态了，想提高的话，强烈建议好好看看。 ADVANCED ASIC CHIP SYNTHESIS中文翻译资料.ppt这也是我极力推荐的，相信学习dc的人都知道原英文文档。这个ppt相当于翻译版，对dc和pt中文详细阐述。 基于DDR SDRAM控制时序分析的模型.pdf 全定制单元时序模型的建立.pdf 这两篇文档是用作建议时序模型的时候用作参考，是我花了小money买的哦。 数字IC设计全程实例.pdf 本文介绍了基于标准单元库的深亚微米数字集成电路的自动化设计流程。此流程从设计的系统行为级描述或RTL 级描述开始，依次通过系统行为级的功能验证，设计综合，综合后仿真，自动化布局布线，到最后的版图后仿真. -i2cinterface.v a section of my own writing verilog code for the I2C interface in the interface used in chip design. Sent to flow through the film, only for reference. debussy and modelsim co-simulation. txt for debussy and modelsim co-simulation reference RTL Coding and Optimization Guide for use with Design Compiler.pdf Mention the number of lectures (1). Wmv Mention the number of lectures (2). Wmv the two videos, and the document is useful for the digital front-end IC designers to improve the design capability. if you think you go to bottleneck, and want to improve, then it is strongly recommended a good look. ADVANCED ASIC CHIP SYNTHESIS Chinese translation of the information. Ppt that is what I strongly recommend, I believe that everyone learning dc knows its original English document. This ppt is equivalent to its translations.It elaborates the dc and pt in Chinese . DDR SDRAM control the timing analysis based on the model. Pdf
Platform: | Size: 20989952 | Author: 喻琪 | Hits:

[VHDL-FPGA-Verilog] c_xapp260

Description: xilinx应用指南xapp260的中文翻译版本。利用 Xilinx FPGA 和存储器接口生成器简化存储器接口。本白皮书讨论各种存储器接口控制器设计所面临的挑战和 Xilinx 的解决方案，同时也说明如何使用 Xilinx软件工具和经过硬件验证的参考设计来为您自己的应用（从低成本的 DDR SDRAM 应用到像 667 Mb/sDDR2 SDRAM 这样的更高性能接口）设计完整的存储器接口解决方案。-The use of Xilinx FPGA and Memory Interface Generator to simplify memory interface. This white paper discusses the various memory interface controller design challenges facing Warfare and Xilinx solutions, but also explains how to use Xilinx Software tools and hardware-proven reference designs to be for your own With (from low-cost DDR SDRAM applications to such as 667 Mb/s This higher performance DDR2 SDRAM interface) design a complete deposit Storage device interface solution.
Platform: | Size: 1123328 | Author: 陈阳 | Hits:

[VHDL-FPGA-Verilog] DDR_controller_verilog

Description: ddr的控制程序，用verilog实现的，非常的具体。-ddr
Platform: | Size: 623616 | Author: 张杰 | Hits:

[VHDL-FPGA-Verilog] doc17414x90

Description: ddr设计控制器，源代码！Verilog代码！-设计控制器，源代码！Verilog代码！
Platform: | Size: 646144 | Author: 张杰 | Hits:

[Software Engineering] DDRcontroller

Description: 对DDR控制器的FPGA实现及其代码和参考注释-verilog source code written to read and write DDR
Platform: | Size: 800768 | Author: 张琦 | Hits:

[VHDL-FPGA-Verilog] ml505_mig_design

Description: Xilinx开发板ML505的DDRII示例程序，使用Verilog，调用MIG，编译环境ISE11.1-Xilinx ML505 development board of DDRII sample program, using Verilog, called MIG, build environment ISE11.1
Platform: | Size: 9332736 | Author: 黑羽·X | Hits:

[VHDL-FPGA-Verilog] ddr

Description: 利用硬件verilog语言实现DDR2功能，对信息快速存储-VERILOG DDR2
Platform: | Size: 316416 | Author: | Hits:

[VHDL-FPGA-Verilog] DDR-SDRAM_IP_core

Description: DDR-SDRAM接口模块verilog源代码，可用作IP核使用，已在FPGA上验证-DDR-SDRAM interface module verilog source code, can be used as IP cores to use, proven
Platform: | Size: 474112 | Author: zyy | Hits:

[VHDL-FPGA-Verilog] DDR2-verilog

Description: Verilog程序设计实例中，DDR部分的程序代码-Verilog programming example, DDR part of the program code
Platform: | Size: 1221632 | Author: 林传正 | Hits:

[VHDL-FPGA-Verilog] DDR_CTRL

Description: DDR Verilog 控制器，quartus 10.1工程。适用Altera Cyclone® III starter board-DDR control quatrus 10.1，Altera Cyclone® III starter board
Platform: | Size: 517120 | Author: Enjob | Hits:

[VHDL-FPGA-Verilog] ddr_model_c3

Description: DDR仿真模型，采用erilong语言，FPGA开发DDR控制器必备-DDR simulation module verilog
Platform: | Size: 9216 | Author: 张雪松 | Hits:

[VHDL-FPGA-Verilog] ddr3_mig8

Description: fpga实现ddr数据收发测试，完整的工程，下载解压后，即可正确运行，已多次验证无误(FPGA DDR data receive and receive test, complete engineering, download and unzip, can run correctly, has been verified many times)
Platform: | Size: 16119808 | Author: 大木瓜 | Hits:

[Documents] 黑金Sparten6开发板Verilog教程V1.6

Description: 黑金spartan的开发板教程，包含了各类接口如spi，uart，vga的用例，以及各项存储器如flash，ddr的操作方法(spartan 6 example design)
Platform: | Size: 19894272 | Author: 爱的分啥 | Hits:
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